1. Field of the Invention
The present invention relates to an extended drain metal oxide semiconductor field effect transistor (EDMOSFET) and a method for fabricating the same, and more particularly, to an EDMOSFET with a source field plate and a method for fabricating the same.
2. Description of the Related Art
FIG. 1 is a sectional view of a conventional EDMOSFET with a source field plate. Referring to FIG. 1, a p-type well region 102 is formed in a p-type semiconductor substrate 100. An n-drift region 104, an n+-source region 106, and a p+-source contact region 108 are formed in an upper region of the p-type well region 102. The n+-source region 106 includes an n-type lightly doped drain (LDD) region 105. An n+-drain region 110 is formed in the nxe2x88x92-drift region 104. The n+-source region 106 and the p+-source contact region 108 are located adjacent to each other, and the n+-source region 106 and the nxe2x88x92-drift region 104 are separated from each other by a predetermined distance.
A gate insulating layer 112 and a gate conductive layer 114 are sequentially deposited on the p-type well region 102 between the nxe2x88x92-drift region 104 and the n+-source region 106. An interlayer dielectric layer 116 is formed to cover a field oxide layer 118 and the gate conductive layer 114, and partially expose the surfaces of the n+-source region 106, the p+-source contact region 108, and the n+-drain region 110. A metal drain electrode 120 is formed to cover the exposed surface of the n+-drain region 110, and a metal source electrode 122 is formed to cover the exposed surfaces of the n+-source region 106 and the p+-source contact region 108.
The metal source electrode 122 extends over the interlayer dielectric layer 116 to overlap with the gate conductive layer 114 and thus it also acts as a metal field plate 124. As a result, as a bias voltage applied between the drain electrode 120 and the metal field plate 124 is increased with increased drain voltage, a high electric field generated at the junction between the p-type well region 102 and the nxe2x88x92-drift region 104 below an edge of the gate conductive layer 114 is decreased, thereby increasing the breakdown voltage of the device.
However, the effect of the metal field plate 124 of suppressing the generation of high electric fields is effective only for 100V or greater high-voltage devices, but almost not for 20-40V medium-voltage devices. This is because the interlayer dielectric layer 116 between the metal field plate 124 and the nxe2x88x92-drift region 104 is as thick as about 600 nm (d1 in FIG. 1). To ensure the metal field plate 124 to effectively suppress generation of the high electric field in medium-voltage devices, there is a need to reduce the thickness d1 of the interlayer dielectric layer 116. However, when the interlayer dielectric layer is formed to have a reduced thickness, almost all manufacturing processes following formation of the metal field plate 124 should be performed at relatively low temperatures. Therefore, the general manufacturing process for CMOS devices cannot be applied to devices operating using medium level voltages that need a thin interlayer dielectric layer.
It is a first objective of the present invention to provide an extended drain metal oxide field effect transistor (EDMOSFET) with a source field plate, which can effectively operate using medium level voltages and can be fabricated by a general manufacturing process for CMOS devices.
It is a second objective of the present invention to provide a method for fabricating an EDMOSFET having a source field plate.
To achieve the first objective of the present invention, there is provided an EDMOSFET comprising: a first-conductivity type semiconductor substrate; a first-conductivity type well region formed in the semiconductor substrate; a second-conductivity type drift region formed in a predetermined upper region of the well region; a heavily doped second-conductivity type drain region formed in a predetermined upper region of the drift region; a heavily doped second-conductivity type source region formed in the predetermined upper region of the well region with a predetermined gap separation from the drift region; a gate insulating layer formed on the surface of the well region between the drift region and the source region; a gate conductive layer formed on the gate insulating layer; a first interlayer dielectric layer covering portions of the surfaces of the source region and the drift regions, and the gate conductive layer; a source field plate formed on the first interlayer dielectric layer; a second interlayer dielectric layer covering the source field plate and partially exposing the surfaces of the source region and the drain region; a source electrode formed in contact with the exposed surface of the source region and electrically connected to the source field plate; and a drain electrode formed in contact with the exposed surface of the drain region.
It is preferable that the first interlayer dielectric layer is formed of a tetraethylorthosilicate (TEOS) layer to a thickness of about 300-600 xc3x85. It is preferable that the source field plate is formed of a polysilicon layer. It is preferable that the second interlayer dielectric layer is formed of a 1500 xc3x85-thick TEOS layer and a 4500 xc3x85-thick borophosphosilicate glass (BPSG) layer.
It is preferable that the EDMOSFET further comprises a gate spacer layer on the sidewall of the gate conductive layer. In this case, the gate spacer layer is preferably formed of a low-temperature oxide layer.
It is preferable that the EDMOSFET further comprises a capacitor including a lower electrode layer, dielectric layer, and upper electrode layer sequentially stacked, wherein the dielectric layer is formed of the same material to the same thickness as the first interlayer dielectric layer, and the upper electrode layer is formed of the same material to the same thickness as the source field plate.
To achieve the second objective of the present invention, there is provided a method for manufacturing an EDMOSFET, the method comprising: (a) on a first-conductivity type semiconductor substrate, forming a well region having the same conductivity type; (b) forming a second-conductivity type drift region, the second-conductivity type being opposite to the first-conductivity type, in a predetermined upper region of the well region; (c) forming a heavily doped first-conductivity type source contact region and a heavily doped second-conductivity type source region in the predetermined upper region of the well region and a heavily doped second-conductivity type drain region in a predetermined upper region of the drift region; (d) forming a gate insulating layer on the surface of the well region between the source region and the drift region; (e) forming a gate conductive layer on the gate insulating layer and a capacitor lower conductive layer on a field oxide layer defining an active region; (f) forming a first interlayer dielectric layer covering the gate conductive layer and a portion of the capacitor lower conductive layer; (g) forming a source field plate and a capacitor upper conductive layer on the first interlayer dielectric layer; (h) forming a second interlayer dielectric layer exposing portions of the surfaces of the source region, the source contact region, the drain region, and the capacitor lower conductive layer; and (i) forming a source electrode in contact with the exposed portions of the source region and the source contact region, a drain electrode in contact with the exposed portion of the drain region, a capacitor upper electrode in contact with the capacitor upper conductive layer, and a capacitor lower electrode in contact with the capacitor lower conductive layer.
It is preferable that steps (f) and (g) comprises: forming the first interlayer dielectric layer on the gate conductive layer and the capacitor lower conductive layer;
forming a polysilicon layer on the first interlayer dielectric layer; forming a photoresist pattern to cover portions of the polysilicon layer to be the source field plate and the capacitor upper conductive layer; and etching the exposed portions of the polysilicon layer using the photoresist pattern as an etch mask.
It is preferable that the first interlayer dielectric layer is formed of a TEOS layer to a thickness of about 300-600 xc3x85. It is preferable that the source field plate is formed of a polysilicon layer. It is preferable that the second interlayer dielectric layer is formed of a 1500 xc3x85-thick TEOS layer and a 4500 xc3x85-thick BPSG layer.